# HP ADS 1.5 User-defined Models User Manual

Brand: HP, Pages: 216, PDF Size: 1.33 MB

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SDD Examples 5-41

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5-42 SDD Examples

Custom Modeling with Symbolically-Defined Devices

Note the following points.

• Each port has two equations, one for the current and one for the charge.

• The capacitance equations were integrated to obtain charge equations:

• The integration is simplified for the first term of C

be since the first term is a

partial derivative, the integration and partial derivative effectively cancel.

• The integration is simplified for the first term in C

bc since the first term is an

exponential, and integration of an exponential is another exponential.

• The other charges are similar in form to the charge given earlier in the

section, “Full Model Diode, with Capacitance and Resistance” on page 5-28.

•The diode() and charge() functions are used to make the equations more

readable and to eliminate the duplication of common expressions.

• Except for one difference, the SDD BJT presented here is identical to the

compiled BJT model built-in to the simulator (in the simulator, the values of V

je

and V

jc are adjusted to reflect the bandgap characteristics of silicon).

• The SDD BJT uses about 55 equations. The built-in BJT model requires over

4500 lines of C code.

• The SDD BJT was written in about one day, and debugged in about one day. The

built-in BJT model required about two weeks to write and another two weeks to

debug.

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SDD Examples 5-43

Examples Summary

•A voltage-controlled nonlinear resistor is described by its i-v relation

• A two-terminal voltage-controlled nonlinear resistor i = I(v) is implemented by

I[1,0] = _v1

•A general nonlinear resistor is described by an implicit i-v relation

• A general two-terminal nonlinear resistor f(i,v) = 0 is implemented by

I[1,0] = f(_i1, _v1)

•A voltage-controlled nonlinear capacitor is described by its q-v relation

• A two-terminal voltage-controlled nonlinear capacitor q = Q(v) is implemented

by

I[1,1] = Q(_v1)

• A two-terminal voltage-controlled device with resistance i = I(v) and charge q =

Q(v) is implemented by

I{[1,0] = I(_v1)

I[1,1] = Q(_v1)

• If a capacitor is specified by a nonlinear capacitance C(v) where

then the corresponding charge is given by

where Q

o is the arbitrary constant of integration.

iIv() =

fiv, ()0. =

qQv(). =

iCv()dv

dt -------

, =

Qv()Cvˆ

()vˆ

Qo+ dvò=

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5-44 SDD Examples

Custom Modeling with Symbolically-Defined Devices

•A current-controlled nonlinear inductor is described by its f-i relation

• A two-terminal current-controlled nonlinear inductor f = F(i) is implemented

by

I[1,0] = _v1

I[1,1] = -phi(_i1)

• If an inductor is specified by a nonlinear inductance L(i) where

then the corresponding flux is given by

where F

o is the arbitrary constant of integration.

• SDD models are easier to write and debug than compiled models, but they are

less efficient during a simulation.

fFi(). =

vLi()

didt ------, =

Fi ()Liˆ

()i ˆ

Fo+ diò=

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Modified Nodal Analysis 5-45

Modified Nodal Analysis

Advanced Design System uses nodal analysis to form the circuit equations. Nodal

analysis is based on Kirchoff ’s current law (KCL) which states that for each node, the

sum of the currents incident to the node is zero.

Suppose a circuit has n+1 nodes and b branches. Let i be the vector of branch

currents. Then KCL can be expressed by the equation

Ai = 0

where A is an n x b matrix called the node incidence matrix. The entries in A are

given by

In nodal analysis, KCL is not applied to the ground node (such an equation yields no

independent information) which explains why A has only n rows. If all the devices in

the circuit are voltage controlled, that is, if the port currents of each device are

completely determined by the port voltages of that device, then the branch current

vector i can be written as

i = g(v)

where v represents the vector of n node voltages and g is a map from IR

n to IRb.

Substituting this equation into the KCL equation yields the node analysis equation

G(v) = 0

where G is a map from IR

n to IRn defined by G(v)= Ag(v). a

ij

1 if branch j enters node i

1 if branch j leaves node i –

0 otherwise è ç

ç

æ

=